1. Field of the Invention
The invention relates to semiconductor memory devices and, more particularly, to a method of forming a metal line of a semiconductor memory device.
2. Related Technology
A formation method of a damascene structure using tungsten (W) as a plug has been employed as a method of forming a metal line of a flash memory device. As the level of integration of devices increases, the design rule decreases, and space between patterns in which lines are formed is reduced, thus making it difficult to secure a capacitance value.
To solve the capacitance problem, it is necessary that the height of a metal layer be lowered in order to decrease a capacitance value in an interfacial junction process. However, a resistance value is increased due to the lowered height of the metal layer. Accordingly, material with a low resistivity characteristic can be formed in the interface in order to maintain the resistance value while securing the capacitance value by decreasing the height of the metal layer.
The material with a low resistivity characteristic can include copper (Cu) used in logics, aluminum (Al) used as a wire material, and the like. However, it is difficult to use aluminum (Al) because of the slurry problem of a subsequent Chemical Mechanical Polishing (CMP) process, such as a tungsten damascene process.
As an alternative method, an attempt is made to form a pattern using a Reactive Ion Etching (RIE) method after aluminum (Al) is formed. The aluminum RIE method includes forming a barrier metal layer, and then sequentially laminating aluminum and an anti-reflection layer. However, this method causes damage to sidewalls of an Al metal layer due to a difference in the etch ratio depending on material and over-etch in a subsequent etch process. Further, voids are generated when a dielectric material is formed due to the damaged sidewalls, degrading reliability.